In a basic form, an N-bit flash analog-to-digital (A/D) converter (hereinafter referred to as “ADC”) has 2N−1 comparators, arranged in cardinal order to compare the same input signal against a respective cardinal order of 2N−1 equally spaced reference voltages. The voltage spacing between each comparator and its adjacent higher and/or lower comparator is typically one least significant bit (LSB) of the N-bit output.
In operation, all of the 2N−1 comparators receive the same sampling clock (typically periodic at a sampling rate) and, at each clock pulse, generate a broadside output of “1s” from all comparators (if any) for which the signal exceeds the reference voltage, and a “0” from all comparators (if any) having higher reference voltages. The broadside output of the 2N−1 comparators is sometimes referred to as “thermometer code” encoding, because it can be visualized as similar to a liquid column thermometer, where the liquid (e.g., mercury) rises to a point corresponding to the temperature.
A decoding logic decodes the broadside of binary outputs to generate a binary N-bit data representing, in the cardinal ordering of the 2N−1 comparators, which from the comparators generating a “1” has the highest reference voltage. Stated differently, if the comparators generating “1s” are considered as a thermometer column, the decoding logic generates a binary N-bit data representing the “top” comparator of the column.
One significant feature of flash ADCs is speed. ADCs enable high speed conversion because, in basic form, each sample requires only one clock. This differs from other known ADC architectures such as, for example, successive approximation (SAR) ADCs that use a plurality of clock cycles to convert the signal.
However the number of comparators required to construct prior art flash ADCs is exponentially related to the number of bits. Simply put, N bits of resolution requires 2N−1 comparators.
As an illustration, a basic 4-bit flash ADC (assuming the output “bit” is binary valued) converts the input into one of 16 levels and, therefore, requires 15 comparators (a zero value does not require a comparator). An 8-bit flash ADC requires 255 voltage comparators. With current state-of-the art A/D technology, economical implementation of 255 comparators and all the required support circuitry in an acceptable size and acceptable power consumption package is readily attained. A 10-bit true flash ADC, meaning 10 bits in a single clock, requires 1023 comparators.
This requirement for 2N−1 comparators causes multiple problems.
One problem is that each comparator requires chip area and, therefore, as a rough estimate, each one bit increase in resolution may require approximately a doubling of the chip area.
Another problem is that clocked comparator circuits have various capacitances, and current flows are required to charge and discharge these capacitances. As a rough estimator, each one bit increase in resolution may approximately double the power dissipation. For reasons well known to persons skilled in the art, these power issues may manifest significantly at higher sampling rates.
Another problem arising from the requirement for 2N−1 comparators is that, for ideal performance (meaning maximum sampling rate and minimal noise and distortion), the input amplifier to a flash ADC must deliver high current at a fast slew rate. The reason is that the input of each of the 2N−1 comparators has a capacitance. A multi-stage, fan-out arrangement of buffers may not be acceptable because these introduce various distortions, and bandwidth reduction. For this reason, it is often preferable when striving for a maximum speed and accuracy flash ADC that a single amplifier output directly connects to all of the signal level comparators. In such instances the input amplifier must effectively drive a load of 2N−1 parallel capacitors.
Still other problems, both additional to and exacerbating of the above example problems of structural overhead (e.g., power dissipation, and input amplifier demands), is that the present requirement for 2N−1 comparators necessarily introduces noise and linearity problems. Basically, each doubling of the number of bits halves the voltage difference between successive comparators. This, in turn, reduces tolerance for comparator inaccuracy, and increases susceptibility to noise-induced error by the comparators. Still further, circuit technologies and design methods directed to controlling such comparator accuracy and noise problems, in addition to direct cost, often require a compromising of ADC cost.
Methods to lessen or ameliorate some of these problems have been identified and, in certain instances, some may be used. All, however, have significant costs.
One example of such methods is the subranging ADC. In a basic form, a subranging ADC performs an N-bit quantizing using a multiple step sequence. Generally, each additional step provides a theoretical increase of one bit of resolution, using substantially the same number of signal level comparators. However, subranging ADCs have costs. Reduced quantizing speed is foremost, and is significant. Each additional step reduces the maximum speed by two. Distortion and noise arising from the lengthened “hold” time of the internal sample-and-hold circuitry is another problem.